Conventional semiconductor memory devices may be classified into volatile memory devices such as DRAM and nonvolatile memory devices such as flash memory.
In case of a conventional volatile memory device, particularly, a DRAM memory device, its integration is basically limited due to a one-transistor one-capacitor (1T-1C) unit cell structure and problems such as increase in an aspect ratio (A/R) of a capacitor and leakage current occur according to the integration. As a result, power required for periodical refresh is consumed to cause limitations in integration and storage capacity per unit cell of the memory device.
A nonvolatile memory device, i.e., a flash memory device has basic problems as follows. A gentle current-voltage (I-V) characteristic curve is formed due to a subthreshold swing (SS) of 60 mV/dec. When data is read, a data error occurs due to a small current sensing margin. In addition, read/write characteristics are degraded due to a high gate voltage and a threshold voltage value varies during read/write operations to cause data distortion. Furthermore, memory characteristics vary depending on duration of use.
Accordingly, through a capacitorless one-transistor (1T) semiconductor memory device as a novel nonvolatile DRAM memory device, there is a need for developing a novel nonvolatile memory device having a more integrated cell structure, a long refresh period according to improved information retention characteristics and decrease in leakage current, and low power consumption that a low operating voltage requires per unit cell structure.
However, it is becoming difficult to keep pace with the high-capacity trend resulting from spread of demand for handheld digital devices and emergence of new digital multifunctional apparatuses in which various functions are combined. In recent years, integration of memory devices has a limitation due to various performance degradations (e.g., decrease in SS value, increase in leakage current, increase in power consumption, etc.) caused by short-channel effect that occurs as conventional memory devices are scaled down. Studies such as technical application of strain engineering, high-k dielectrics, and metal gate have been conducted to overcome the above problems. However, complex processes and high costs are still problematic.
Moreover, a conventional volatile DRAM memory device or a conventional flash memory device has a structure that is capable of utilizing only its own characteristics. Hence, when volatile or nonvolatile operation characteristics are selectively required, memory devices may not be flexibly utilized. This is a basic problem of the conventional volatile DRAM memory device or the conventional flash memory device.
Accordingly, there is a need for developing a novel memory device which may be scaled down and integrated with a simple structure, reduce leakage current to have features of low power and high efficiency, and secure a sufficient read sensing margin even in a narrow memory window. In this regard, there are needs for a low applied voltage during write/erase operations, operating voltage characteristics required per low unit cell structure in which a sufficient current sensing margin may be secured even in a narrow memory window due to a high on-off current ratio and a low subthreshold swing (SS), and capable of implementing volatile/nonvolatile operation characteristics in one device. Moreover, there is a pressing need for developing a nanostructure-based device having superior electrical/physical/structural characteristics.